1. Field of the Invention
The present invention generally relates to circuit simulation methods and, in particular, a method for selecting pertinent subcircuits from a VLSI/ULSI circuit design in the simulation and characterizing of the VLSI/ULSI circuit design.
2. Description of the Prior Art
A modern day integrated circuit design may have millions of transistors. Simulation of these Very Large Scale Integrated (VLSI) circuit designs or Ultra Large Scale Integrated (ULSI) circuit designs becomes a time consuming proposition requiring not only a high speed computer but complex simulation software as well.
In conducting these simulations, all of the transistors and distinct circuit components along with their interrelationships as defined by the user (typically in a SPICE netlist) are loaded into computer memory and simulated. Given the size of these circuit designs, the computer performing the simulation necessarily has to be a fairly powerful computer with substantial amount of memory. Even with such a computer, the simulation of the circuit design may still require many hours to many days of computing time.
When circuit designs continue to increase in size, the traditional simulation methods and software tools become impractical due to the time required in simulating these circuit designs. Thus, there is a need for novel methods for simulating large circuit designs.